Distribution of CAD Tools for Testing

We have developed CAD tools for testing and distributed the source code for four tools (two test pattern generators and two fault simulators) to over 140 universities, research institutions, and companies on five continents. The tools have been used for various research and teaching purposes at numerous universities. Our tools have been particularly popular in academia owing to ease of use. The usefulness of our tools for research and teaching is well described by Professor Edward McCluskey from Stanford University, who is a world-wide known scholar in VLSI testing. His comment in response to a user survey is quoted below:

"Your tools were very important to both my teaching and research programs. They were used extensively, even though we had several commercial tools available. There was a surprising level of satisfaction with your tools -- surprising because all programs have difficulties, but I received very few complaints about your tools. I would like to thank you for making a very important contribution to our activities and encourage you to continue your excellent work."

In addition to the research in fault simulation and test generation, users reported that our tools have been used for research in built-in self-test, fault diagnosis, test response compression and several other topics. Our tools are also used for teaching various subjects such as VLSI testing, fault-tolerant computing, logic design, and logic synthesis. The tools are written in the C language and run on workstations in UNIX environment. Some users ported our tools to personal computers in Linux. All our tools are easy to install and require no maintenance.

We appreciate the financial support provided by the National Science Foundation for the development and improvement of our tools. We greatly acknowledge the support and the encouragement of Program Director Dr. Robert B. Grafton of the NSF. With his support, all these good things have been possible.

List of Tools Distributed:

The source code for two test pattern generators and two fault simulators listed below have been distributed.

ATALANTA (version 2.0) Automatic test pattern generator for combinational circuits
FSIM (version 1.1) Fault simulator for combinational circuits
SOPRANO (version 1.1) Automatic test pattern generator for stuck-open faults in CMOS combinational circuits
HOPE (version 2.0) Parallel fault simulator for sequential circuits

 

 

Comments to: ha@vt.edu

 

 

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