# ###########################################################
#
# Filename	.synopsys_dc.setup 
# Synopsis	Setup file for Synopsys Design Compiler
# Owner		MICS Lab, Virginia Tech, Blacksburg
# Author	Jeannette Djigbenou (JDDJIG01@VT.EDU)
#               Hetaswi Vankani (HETASWI@VT.EDU)
# Date		September 14, 2013
# 
# Tool		Design Compiler Y-2006.06-SP2
# Command 	dc_shell-xg-t 
#
# ###########################################################

# Standard Information
set company "MICS Lab, Virginia Tech"
set designer  "Hetaswi Vankani (hetaswi@vt.edu)"
set run_dir [pwd]
echo "Location of .synopsys_dc.setup: $run_dir"

# Configuration Settings
# search_path is used to search for libraries and other files
set search_path {. ./libs ../tutorials/libs /software/Synopsys/Y-2006.06-SP2/libraries/syn}

# target_library is the library or list of libraries we want the design
# compiler to target as a result of synthesis. Cell library in db format 
set target_library [list tcbn65gplusbc0d88.db tpdn65gpgv2od3_sdbc.db]

# Libraries the design should be linked. Typically the combined list of
# synthetic_library and target_library. synthetic_library are not used
# here, so it's default target_library
set link_library [list tcbn65gplusbc0d88.db tpdn65gpgv2od3_sdbc.db]

# symbol_library is the list of library that has grephical symbol information
set symbol_library {"vtvt_tsmc250.sdb" "basic.sdb" "NCSU_Analog_Parts.sdb" "US.8ths.sdb"}

# Location for intermediate files
#WORK > DEFAULT
#DEFAULT : ./work
#vtvt_tsmc250 : ./vtvt_tsmc250

# Turn tri state nets from tri to wire
set verilogout_no_tri "true"

# EDIF is a vendor neutral format. Retain the setting for it.
# Read Symbol
set edifin_lib_route_grid 1024
set vhdlout_use_packages {IEEE.std_logic_1164 IEEE.std_logic_arith IEEE.std_logic_textio vtvt_tsmc180.components}


# EDIF read symbol library variables
# EDIF variables for Importing Special Connectors for Composer
      set edifin_lib_in_port_symbol "ipin"
      set edifin_lib_out_port_symbol "opin"
      set edifin_lib_inout_port_symbol "iopin"

      set edifin_lib_in_osc_symbol "iosc"
      set edifin_lib_out_osc_symbol "oosc"
      set edifin_lib_inout_osc_symbol "oosc"

      set edifin_lib_logic_1_symbol "vdd"
      set edifin_lib_logic_0_symbol "vss"

# EDIF variables for Importing a Bus Ripper from Composer
      set edifin_lib_ripper_bits_property "schPatchExpr"
      set edifin_lib_ripper_bus_end "bus_end"
      set edifin_lib_ripper_cell_end "ripper"
      set edifin_lib_ripper_view_name "symbol"
      set edifin_lib_route_grid 1024

# EDIF variables for Importing Sheet Templates from Composer
      set edifin_lib_templates {{A,landscape,Asize},{A,portrait,Asize.book}, \
      {B,landscape,Bsize},{C,landscape,Csize},{D,landscape,Dsize}, \
      {E,landscape,Esize},{F,landscape,Fsize}}

      # Bus Naming variables
      set bus_naming_style {%s[%d]}
      set bus_dimension_separator_style {][}
      set bus_range_separator_style ":" 
      set bus_extraction_style {%s[%d:%d]}
      set bus_minus_style "-%d"
      set edifout_no_array "false"

      # Read design variagles
      set edifin_autoconnect_offPageConnectors "true"
      set edifin_delete_empty_cells "true"
      set edifin_delete_ripper_cells "true"

      # Power and Ground variables
      set edifin_ground_net_name "vss!"
      set edifin_ground_net_property_name ""
      set edifin_ground_net_property_value   ""

      set edifout_ground_name   "vss!"
      set edifout_ground_net_name   "vss!"
      set edifout_ground_net_property_name   ""
      set edifout_ground_net_property_value   ""
      set edifout_ground_pin_name   "vss!"

      set edifin_power_net_name   "vdd!"
      set edifin_power_net_property_name   ""
      set edifin_power_net_property_value   ""

      set edifout_power_name   "vdd"
      set edifout_power_net_name   "vdd!"
      set edifout_power_net_property_name   ""
      set edifout_power_net_property_value   ""
      set edifout_power_pin_name   "vdd!"
      set edifout_power_and_ground_representation   "net"


      # Net to Port Connection variables
      set edifin_autoconnect_ports   "true"
      set compile_fix_multiple_port_nets   "true"
      set gen_match_ripper_wire_widths   "true"
      set edifout_name_rippers_same_as_wires   "false"
      set link_force_case   "case_insensitive"
      set single_group_per_sheet   "true"
      set use_port_name_for_oscs   "false"
      set write_name_nets_same_as_ports   "true"

      # Output variables
      set edifout_netlist_only   "false"
      set edifout_external   "true"
      set edifout_translate_origin   "center"
      set edifout_display_instance_names   "false"
      set edifout_display_net_name   "false"
      set edifout_target_system   "cadence"
      set edifout_instantiate_ports   "true"
      set edifout_pin_name_property_name   "pinName"
      set edifout_designs_library_name   "SYNOPSYS"