Design Vision - Verilog Logic Synthesis Tool

Authors: Jinsik Yun, Dr. Dong S. Ha

This tutorial shows a Verilog synthesis process using Design Vision. After that, it will show simulation methos for synthesized netlist. You have to follow these instructions in order to minimize any setup errors. Note that this tutorial is based on the vtvt_tsmc180 library.

1. Synthesis for generic gates

Please open '.synopsys_dc.setup' and change 'Bus Naming variables' section in that file as exactly same as the below table.

Before	After
set bus_naming_style "%s<%d>" set bus_dimension_separator_style "><" set bus_extraction_style "%s<%d:%d>"	set bus_naming_style "%s[%d]" set bus_dimension_separator_style "][" set bus_extraction_style "%s[%d:%d]"

Type 'design_vision' at the prompt in <your_pjt_dir>. You can see several error messages due to the change of .synopsys_dc.setup at the previous stage. However you can simply ignore it.
In 'Design Vision' window,
- File -> Read... -> open 'cnt_updown.v'.
- Click updown_counter in the 'Logical Hierarchy' window and click 'Creat Design Schematic'
You can see the synthesized logic design using generic gates.

2. Synthesis for vtvt_tsmc_library

In 'Design Vision' window,
- Click updown_counter in the 'Logical Hierarchy' window
- Hierarchy -> Uniquify -> Hierarchy... -> click OK button leaving all input blank.
- Design -> Compile Design... -> click OK button (make sure the Map design option is selected)
Click updown_counter in the 'Logical Hierarchy' window and click 'Creat Design Schematic'
You can see the synthesized logic design using vtvt tsmc library gates.

3. Extract Netlist

File -> Save As... -> type 'cnt_updown_syn' in 'File name' field
-> select 'VERILOG(v)' in the Format field. -> click 'Save' button
You can see the newly generated 'cnt_updown_syn.v' in <your_pjt_dir>.

4. Simulating a Synthesized Netlist

Type these commands sequetially. (Before doing that, I encourage you to delete all contents within 'work' directory in order to make sure that you use newly-compiled designs)
- vlogan cnt_updown_syn.v
- vlogan tb_cnt_updown.v
- vcs tb_cnt_updown
  (Please make sure that tb_cnt_updown is the top module name in this commands)
if you have 'version error' or 'incompatible error', please refer to FAQ section.
You can follow the same instruction of Execute Simulation part of VCS-Verilog Logic Simulation.

5. Design Compiler shell and Optimizing the clock skew

Actually Desgin Vision is just a GUI version of Design Compiler shell. So if you use this script cnt_updown_syn.scr, you can directly use Design Compiler.
Type dc_shell-xg-t in UNIX prompt. Design Compiler starts.
- Make sure that you have this command create_clock "clk" -name clk -period 10000 in the cnt_updown_syn.scr
  - Through this create_clock command, we can see the critical path briefly and optimize the clock skew
Type source cnt_updown_syn.scr at the DC Shell prompt.
- Then Design Compiler optimize the clock path in order to reduce clock skew while synthesizing the verilog code.
- You can see critical path information and critical timing information as well. Refer to the picture below.
  
  Note:This example is from another design not cnt_updown.v
The Verilog synthesized design cnt_updown_syn.v is generated.
- This is slightly bigger than the result of previous step since Design Compiler inserted a few gates in order to compensate the clock skew.